1. Introduction
This invention relates to a process for fabrication of printed circuit boards. More particularly, this invention relates to a metallization process for printed circuit board manufacture using a carbonaceous coating as a conductive layer for direct electroplating. More specifically, this invention has for its object a direct plate process involving fewer processing steps which process provides a printed circuit board exhibiting a significantly reduced incidence of interconnect defects.
2. Description of the Prior Art
Nonconducting surfaces are conventionally metallized by a sequence of steps comprising catalysis of the surface of the nonconductor to render the same catalytic to electroless metal deposition followed by contact of the catalyzed surface with an electroless plating solution that deposits metal over the catalyzed surface in the absence of an external source of electricity. Metal plating continues for a time sufficient to form a metal deposit of the desired thickness. Following electroless metal deposition, the electroless metal deposit is optionally enhanced by electrodeposition of metal over the electroless metal coating to a desired thickness. Electrolytic deposition is possible because the electroless metal deposit serves as a conductive coating that permits electroplating.
Catalyst compositions useful for electroless metal plating are known in the art and disclosed in numerous publications including U.S. Pat. No. 3,011,920, incorporated herein by reference. The catalyst of this patent consists of an aqueous suspension of a tin/noble catalytic metal colloid. A surface treated with such a catalyst promotes the generation of an electrolessly formed metal deposit by the oxidation of a reducing agent in an electroless plating solution catalyzed by the catalytic colloid.
Electroless plating solutions are aqueous solutions containing both a dissolved metal and a reducing agent in solution. The presence of the dissolved metal and reducing agent together in solution results in plate out of the metal in contact with a catalytic metal tin catalyst. However, the presence of the dissolved metal and reducing agent together in solution may also result in solution instability and indiscriminate deposition of metal on the walls of containers for such plating solutions. This may necessitate interruption of the plating operation, removal of the plating solution from the tank and cleaning of tank walls and bottoms by means of an etching operation. Indiscriminate deposition may be avoided by careful control of the plating solution during use and by use of stabilizers in solution which inhibit indiscriminate deposition, but also retard plating rate.
Attempts have been made in the past to avoid the use of an electroless plating solution by a direct plating process whereby a metal may be deposited directly over a treated nonconducting surface. One such process is disclosed in U.S. Pat. No. 3,099,608, incorporated herein by reference. The process disclosed in this patent involves treatment of the nonconductive surface with a tin-palladium colloid which forms an essentially nonconductive film of colloidal palladium particles over the nonconducting surface. This may be the same tin-palladium colloid used as a plating catalyst for electroless metal deposition. For reasons not fully understood, it is possible to electroplate directly over the catalyzed surface of the nonconductor from an electroplating solution though deposition occurs by propagation and growth from a conductive surface. Therefore, deposition begins at the interface of a conductive surface and the catalyzed nonconductive surface. The deposit grows epitaxially along the catalyzed surface from this interface. For this reason, metal deposition onto the substrate using this process is slow. Moreover, deposit thickness is uneven with the thickest deposit occurring at the interface with the conductive surface and the thinnest deposit occurring at a point most remote from the interface.
An improvement in the process of U.S. Pat. No. 3,099,608 is described in U.K Patent No. 2,123,036 B, incorporated herein by reference. In accordance with the process described in this patent, following catalysis, a surface is electroplated from an electroplating solution containing an additive that is said to inhibit deposition of metal on the metal surface formed by plating without inhibiting deposition on the metallic sites over the nonconductive surface. In this way, there is said to be preferential deposition over the metallic sites with a concomitant increase in the overall plating rate. In accordance with this patent, the metallic sites are preferably formed in the same manner as in the aforesaid U.S. Pat. No. 3,099,608xe2x80x94i.e., by immersion of the nonconductive surface in a solution of a tin-palladium colloid. The additive in the electroplating solution responsible for inhibiting deposition is described as one selected from a group of dyes, surfactants, chelating agents, brighteners and leveling agents. Many of such materials are conventional additives for electroplating solutions.
There are limitations to the above process. Both the processes of the U.S. and U.K. patents for electroplating require conductive surfaces for initiation and propagation of the electroplated metal deposit. For this reason, the processes are limited in their application to metal plating solutions of nonconducting substrates in areas in close proximity to a conductive surface. In addition, in practice it has been found that the surface provided with metallic sites is not robust and does not stand up to those chemical treatment compositions used prior to the step of electroplating. For this reason, when the process is used for the manufacture of printed circuit boards, void formation is a significant problem resulting in rejection of circuit boards manufactured by the process.
Improvements in processes for direct electroplating of nonconductors overcoming the deficiencies in the processes disclosed in U.S. Pat. No. 3,099,608 and in U.K. Pat. No. 2,123,036 are known. One such process is disclosed in U.S. Pat. Nos. 4,895,739; 4,919,768; 4,952,286; and 5,276,290, each incorporated herein by reference. In accordance with the processes of these patents, an electroless plating catalyst, such as that disclosed in the above referenced U.K. patent, is treated with an aqueous solution of a chalcogen, such as a sulfur solution, to convert the catalyst surface to a chalcogenide surface. By conversion of the surface to the chalcogenide conversion coating, the coating formed is both more robust and more conductive and electroless plating catalyst does not desorb from the surface during metallization. Consequently, in accordance with the process of said patents, it is possible to form printed circuit boards using formulations that would otherwise attack the catalyst layer such as those solutions used in pattern plating processes.
The processes of the aforementioned patents provide a substantial improvement over the process of the U.K. patent. However, it has also been found that treatment of an absorbed catalytic metal on a substrate having both nonconducting portions and metallic portions, such as a printed circuit board substrate, with a sulfide solution results in a formation of a sulfide on metal surfaces in contact with the solution of the sulfide precursor solution. Therefore, if the process is used in the manufacture of printed circuit boards, both the catalytic metal and the copper cladding or conductors of the printed circuit board base material are converted into a tenaciously adherent sulfide. If the copper sulfide is not removed prior to electroplating, it may reduce the bond strength between the copper and a subsequently deposited metal over the copper.
An alternative method for direct electroplating of nonconductors is disclosed in U.S. Pat. No. 4,619,741 incorporated herein by reference. In accordance with the procedures of this patent, a nonconductive substrate is coated with a dispersion of carbon black and then dried. The coating is removed from copper surfaces where coating residues are undesired and the remaining portions of the substrate are plated using procedures similar to those described in the aforesaid references. There are several problems inherent in this procedure. For example, carbon black is a poor conductor of electricity and consequently, before forming the carbon black dispersion, in practice, it is believed that the carbon black particles must be treated with an organic ionomer or polymer to enhance conductivity. In addition, during processing and prior to electroplating, the coating formed from the carbon black dispersion is only poorly adherent to the underlying substrate and has a tendency to flake off of the substrate prior to the plating step. This results in void formation during plating. In addition, because of the poor adhesion of the coating to the substrate, subsequent to plating, there is a tendency for the metal deposit to separate from the substrate. This can lead to interconnect defects between a metallized hole and an innerlayer in multilayer printed circuit fabrication. Finally, carbon black is suspected to be carcinogenic to humans.
A more recently utilized direct plate process for metallizing the walls of hole-walls employs dispersions of graphite for the formation of a conductive coating. The use of graphite to form conductive coatings on through-hole walls is known and disclosed in U.S. Pat. No. 2,897,409 incorporated herein by reference. Current processes are disclosed, for example, in U.S. Pat. Nos. 4,619,741; 5,389,270 and 5,611,905, each incorporated herein by reference. In accordance with procedures described in these patents, a dispersion of carbon black or graphite is passed through the through-holes to form a coating of the dispersion on the through hole-walls. The coating is dried to yield a conductive layer of the carbon black or graphite which is sufficiently conductive for electroplating in a conventional manner.
The above processes find substantial use in processes for the manufacture of double sided and multilayer printed circuit boards. A typical process for the manufacture of a multilayer printed circuit board using graphite coatings, excluding water rinses, includes the steps of solvent pretreatment to soften the epoxy circuit board substrate, treatment with an oxidizing agent such as a permanganate solution to form a porous structure and to activate the surface of the epoxy substrate, treatment with a neutralizer to remove permanganate residue, an optional treatment step with a glass etchant, treatment with a solution of a charge modifier to cause adsorption of a subsequently applied graphite layer, formation of the graphite layer by immersion of the substrate in an aqueous graphite dispersion, several drying steps to bond the graphite coating to the epoxy surface, treatment with a microetchant to remove graphite from copper surfaces without removing the same from epoxy surfaces, pattern formation and plating. The overall process is unduly long in the number of processing steps. In addition, it has been found that the process results in a significant number of interconnect defects (ICDs) and voids in the finished circuit resulting in disposal or reworking of the boards containing these defects.
It would be highly desirable to develop a process that reduces the number of processing steps and further reduces the incidence of interconnect and coverage defects. In particular, it would be highly desirable to reduce the incidence of these defects while reducing the overall processing sequence.
The present invention is directed to an improved process for the direct electroplating of a printed circuit board substrate using a dispersion of carbon black or graphite particles, hereinafter referred to collectively as a carbonaceous coating or a carbonaceous dispersion as the context so requires. In accordance with the invention, following treatment with a permanganate solution and before formation of a carbonaceous coating, a single treatment solution is used to replace prior art solutions used to neutralize and remove permanganate residue and charge modify the surface of a circuit board substrate. The single solution contains a hydroxyl substituted lower molecular weight amine, a polyelectrolyte and an organic acid.
Though the subject invention provides the advantage of combining several treatment solutions into a single solution thereby reducing the number of processing steps, for reasons not fully understood, the invention also significantly reduces the incidence of interconnect defects and voids in circuit manufacture.